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HANBit
HMS51232M4L
HAN BIT
SRAM MODULE 2Mbyte (512K x 32-Bit), SIMM 5V Part No.
LOW POWER, 72-Pin
HMS51232M4L
GENERAL DESCRIPTION
The HMS51232M4L is a static random access memory (SRAM) module containing 524,288 words organized in a x32-bit configuration. The module consists of four 512K x 8 SRAMs mounted on a 72-pin, single-sided, FR4printed circuit board. The HMS51232M4L also support low data retention voltage for battery back-up operations with low data retention current. Four chip enable inputs, (/CE_UU1, /CE_UM1, /CE_LM1 and /CE_LL1) are used to enable the module's 4 bytes independently. Output enable (/OE) and write enable (/WE) can set the memory input and output. Data is written into the SRAM memory when write enable (/WE) and chip enable (/CE) inputs are both LOW. Reading is accomplished when /WE remains HIGH and /CE and output enable (/OE) are LOW. For reliability, this SRAM module is designed as multiple power and ground pin. All module components may be powered from a single +5V DC power supply and all inputs and outputs are fully TTL-compatible.
FEATURES
Access time : 55, 70ns High-density 2MByte design High-reliability, low-power design Single +5V 0.5V power supply Low data retention voltage : 2V(min) Three state output and TTL-compatible FR4-PCB design Low profile 72-Pin SIMM
Vss A3 A2 A1 A0 Vcc A11 /OE A10 Vcc NC /CE_LL1 DQ7 DQ0 DQ1 DQ2 DQ6 DQ5 DQ4 DQ3 A15 A17 /WE A13 Vcc DQ8 DQ9 DQ10 NC Vcc /CE_LM1 DQ15 DQ14 DQ13 DQ12 DQ11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
PIN ASSIGNMENT
A18 A16 Vss A6 Vcc A5 A4 Vcc NC /CE_UM1 DQ23 DQ16 DQ17 DQ18 DQ22 DQ21 DQ20 DQ19 Vcc A14 A12 A7 Vcc A8 A9 DQ24 DQ25 DQ26 NC /CE_UU1 DQ31 DQ30 DQ29 DQ28 DQ27 Vss 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
OPTIONS
Timing
55ns access 70ns access
MARKING
-55 -70 M
Packages
72-pin SIMM
72-Pin SIMM TOP VIEW
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HANBit FUNCTIONAL BLOCK DIAGRAM
32 DQ0 - DQ31 A0 - A18 19 A0-18 DQ 0-7 /WE /OE
HMS51232M4L
U1
/CE
/CE_UU1 A0-18 DQ 8-15 /WE /OE
U2
/CE
/CE_UM1 A0-18 DQ16-23 /WE /OE
U3
/CE
/CE_LM1 A0-18 DQ24-31 /WE /OE /WE /OE
U4
/CE
/CE_LL1
TRUTH TABLE
MODE STANDBY NOT SELECTED READ WRITE /OE X H L X /CE H L L L /WE X H H L DQ HIGH-Z HIGH-Z Dout Din POWER STANDBY ACTIVE ACTIVE ACTIVE
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HANBit ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN,OUT VCC PD TSTG
HMS51232M4L
RATING -0.5V to +7.0V -0.5V to +7.0V 4W -65oC to +150oC
Operating Temperature TA 0oC to +70oC Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage * SYMBOL VCC VSS VIH VIL MIN 4.5V 0 2.2 -0.5*
( TA=0 to 70 o C ) TYP. 5.0V 0 MAX 5.5V 0 Vcc+0.5V** 0.8V
VIL(Min.) = -2.0V (Pulse Width 10ns) for I 20 mA
** VIH(Min.) = Vcc+2.0V (Pulse Width 10ns) for I 20 mA
DC AND OPERATING CHARACTERISTICS (1)(0oC TA 70 oC ; Vcc = 5V 0.5V )
PARAMETER Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage * Vcc=5.0V, Temp=25 oC TEST CONDITIONS VIN = Vss to Vcc /CE=VIH or /OE =VIH or /WE=VIL VOUT=Vss to VCC IOH = -4.0mA IOL = 8.0mA SYMBO L ILI IL0 VOH VOL MIN -4 -4 2.4 0.4 MAX 4 4 UNITS A A V V
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HANBit DC AND OPERATING CHARACTERISTICS (2)
HMS51232M4L
MAX DESCRIPTION Power Supply Current:Operating Power Supply Current:Standby TEST CONDITIONS IIO=0mA,/CE=VIL, VIN=VIL or VIH, Read /CE=VIH, Other inputs=VIL or VIH /CEVcc-0.2V, inputs=0~Vcc Other SYMBOL lCC lSB lSB1 -55 60 12 400 -70 60 12 400 UNIT mA mA A
CAPACITANCE
DESCRIPTION Input /Output Capacitance Input Capacitance TEST CONDITIONS VI/O=0V VIN=0V SYMBOL CI/O CIN MAX 32 40 UNIT pF pF
* NOTE : Capacitance is sampled and not 100% tested
AC CHARACTERISTICS (0oC TA 70 oC ; Vcc = 5V 0.5V, unless otherwise specified)
TEST CONDITIONS
PARAMETER Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load * See test condition of DC and Operating characteristics
VALUE 0.8 to 2.4V 5ns 1.5V CL=100pF + 1TTL
CL*
* Including scope and jig capacitance
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HANBit Electronics Co.,Ltd.
HANBit READ CYCLE
-55 PARAMETER Read Cycle Time Address Access Time Chip Select to Output Output Enable to Output Output Enable to Low-Z Output Chip Enable to Low-Z Output Output Disable to High-Z Output Chip Disable to High-Z Output Output Hold from Address Change
SYMBOL
HMS51232M4L
-70 UNIT MAX MIN 70 55 55 25 70 70 35 5 10 20 20 0 0 10 25 25 MAX ns ns ns ns ns ns ns ns ns
MIN tRC tAA tCO tOE tOLZ tLZ tOHZ tHZ tOH 5 10 0 0 10 55
WRITE CYCLE
-55
SYMBOL
PARAMETER Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End of Write to Output Low-Z
-70 MAX MIN 70 60 0 60 50 0 20 0 30 0 5 25 MAX
UNIT ns ns ns ns ns ns ns ns ns ns
MIN tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 55 45 0 45 40 0 0 25 0 5
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HANBit TIMING DIAGRAMS
HMS51232M4L
TIMING WAVEFORM OF READ CYCLE( Address Controlled) ( /CE = /OE = VIL , /WE = VIH)
tRC Address tAA tOH Data out
Previous Data Valid Data Valid
TIMING WAVEFORM OF READ CYCLE (/WE = VIH )
tRC Address tAA /CE tLZ(4) /OE tOLZ Data Out High-Z
Data Valid
tHZ(3,4) tCO tOHZ tOE tOH
Notes (Read Cycle)
1. /WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ (max.) is less than tLZ (min.) both for a given device and from device to device.
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HANBit Electronics Co.,Ltd.
HANBit
HMS51232M4L
TIMING WAVEFORM OF WRITE CYCLE ( /WE Controlled )
tWC
Address
tAW tWR(5)
/OE
tCW(3)
/CE
tAS(4) tWP(2)
/WE
tDW tDH High-Z Data Valid tOHZ tOW High-Z
Data In
Data Out
TIMING WAVEFORM OF WRITE CYCLE ( /CE Controlled )
tWC
Address
tAW tCW(3) tWR(5)
/CE
tAS(4)
/WE
tWP(2) tDW tDH Data Valid
Data In
Data Out
High-Z
Notes( Write Cycle)
1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among /CE going low and /WE going low : A write ends at the earliest transition among /CE going high and/WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CE going low to the end of write.
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HANBit
HMS51232M4L
4. tAS is measured from the address valid to the beginning of wirte. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as/CE, or /WE going high.
FUNCTIONAL DESCRIPTION
/CE H L L L /WE X* H H L /OE X H L X MODE Not Select Output Disable Read Write I/O PIN High-Z High-Z DOUT DIN SUPPLY CURRENT l SB, l SB1 lCC lCC lCC
Note: X means Don't Care
DATA RETENTION CHARACTERISTICS* (TA = 0 to 70 ])
PARAMETER VCC for Data Retention Data Retention Current SYMBOL VDR IDR TEST CONDITION /CE;VCC-0.2V VCC=3.0V, /CE;VCC-0.2V VIN Data Retention Set-up Time Recovery Time * L-Version Only tSDR tRDR MIN 2 MAX 5.5 50 UNIT V A
;V
CC-0.2V
or VIN
:0.2V
See Data Retention Wave forms(below)
0 5
-
ns ns
DATA RETENTION WAVEFORM 1 (/CE Controlled)
tSDR Data Retention Mode Vcc 4.5V 2.2V VDR tRDR
/CE Vss /CE/Vcc- 0.2V
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HANBit Electronics Co.,Ltd.
HANBit
HMS51232M4L
PACKAGING INFORMATION
SIMM Design
108.20 mm 3.18 mm TYP(2x)
16 mm 6.35 mm
1
72
2.03 mm 1.02 mm 6.35 mm 95.25 mm 1.27 mm 3.34 mm
0.25 mm MAX
2.54 mm MIN
1.290.08mm
Gold: 1.040.10 mm 1.27 Solder: 0.9140.10 mm
(Solder & Gold Plating Lead)
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HANBit Electronics Co.,Ltd.
HANBit
HMS51232M4L
ORDERING INFORMATION
1 2 3 4 5 6 7 8
HMS
HANBit Memory Modules SRAM
512 32 M 4L-15
15ns Access Time Component, Low Power SIMM x32bit 512K
1. - Product Line Identifier HANBit ------------------------------------------------------- H 2. - Memory Modules 3. - SRAM 4. - Depth : 512K 5. - Width : x 32bit 6. - Package Code SIMM ------------------------------------------------------- M ZIP ------------------------------------------------------- Z 7. - Number of Memory Components, Low Power -------L 8. - Access time 10 ----------------------------------------------------------- 10ns 12 ----------------------------------------------------------- 12ns 15 ----------------------------------------------------------- 15ns 17 ----------------------------------------------------------- 17ns 20 ----------------------------------------------------------- 20ns
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